Electrically rewritable nonvolatile semiconductor memory (flash memories) are known in which a floating gate electrode and a control gate electrode are stacked on a semiconductor substrate and charge is exchanged between the floating gate electrode and the semiconductor substrate by the tunnel effect to cause writing or erasure (JP-A-2-10597).
FIG. 15 is a schematic diagram of a NAND memory which is one type of electrically rewritable nonvolatile semiconductor memory. In the NAND memory, a laminated gate region d consisting of a floating gate electrode FG, an inter-gate insulating film e, and a control gate electrode CG is formed on the surface of a semiconductor substrate a via a tunnel insulating film f which is an insulating film through which tunnel current can flow. A channel region c is formed in a surface portion, located under the laminated gate region d, of the semiconductor substrate a. An impurity source/drain region (diffusion layer) b is formed in a surface portion, located between adjoining channel regions c, of the semiconductor substrate a. The laminated gate region d, the channel region c, and the source/drain regions b constitute a memory cell. Charge is written to the floating gate electrode FG from the semiconductor substrate a by utilizing the quantum mechanical tunnel effect. Information is read out by utilizing the fact that the amount of current flowing through the surface of the semiconductor substrate a depends on the presence/absence of charge in the floating gate electrode FG. Charge is erased by drawing the charge from the floating gate electrode FG into the semiconductor substrate a by utilizing the quantum mechanical tunnel effect. Symbols WL0-WL3 denote four word lines which are connected to the control gate electrodes CG of the memory cells, respectively.
The above nonvolatile semiconductor memory has the following problems. To produce a larger-capacity nonvolatile semiconductor memory, a larger number of memory cells forms in the same chip area by decreasing the length of the channel regions c and the interval between the channel regions c. However, as a result of such increase in the degree of miniaturization, the channel regions c may come too close to each other and adjoining channel regions c may interfere with each other through capacitive coupling, resulting in an erroneous operation. Further, if the interval between the channel regions c is too small, the laminated gate regions d may become too high relative to the interval between the channel regions c (see FIG. 15), in which case it is difficult to introduce a sufficient amount of impurity into the source/drain regions b. As a result, it is now becoming difficult to obtain a sufficiently large read current in the nonvolatile semiconductor memory.